The present invention relates generally to integrated circuit (IC) design, and more particularly to a bias circuit for sense amplifiers.
A sense amplifier (SA) is an instrument to read data from a memory cell by comparing the memory cell state with a known state. If the memory cell state is higher than the known state, the SA may output a “1”, for instance, and if the memory cell state is lower than the known state, the SA may output a “0” instead. In SA design, a bias circuit is intended to set and maintain a direct current (DC) bias point for the SA, allowing it to operate at an appropriate point in the SA's transfer characteristic. Thus the bias circuit must provide bias stability when there are variations in input signals, circuit parameters, or circuit conditions. The circuit parameters may be affected by manufacturing processes. The circuit conditions include temperature and voltage under which the SA is operating. The bias circuit used for the SA will have significant effect on the operation of the SA.
FIGS. 1A and 1B are schematic diagrams illustrating two conventional bias circuits 100 and 150. Referring to FIG. 1A, NMOS transistors 103 and 113 provide bias for NMOS transistors 106 and 116. For stable and linear operations, the NMOS transistors 106 and 116 are both biased to operate in a saturation region. When in a saturation region and in an ideal situation, the NMOS transistor 116 may be viewed as a resistive load, and the NMOS transistor 106 functions as a constant current source, then a voltage at node A becomes a constant voltage between a positive power supply voltage (Vcc) and a ground (GND) at node A. If the NMOS transistor 106 and 116 are of the same size, then the voltage at node A equals one half of the Vcc.
Referring to FIG. 1B, the load NMOS transistors 113 and 116 are replaced by two resistors 153 and 156, respectively. But the bias circuit 150 of FIG. 1B operates just the same as the bias circuit 100 of FIG. 1A. Unfortunately, in the real world, situations are never ideal. Conditions such as non-linear saturation of the NMOS transistors 103 and 106, process variations or voltage/temperature fluctuations, all make the voltage at node A unstable. Most important is that the process, voltage and temperature fluctuations is unpredictable, and the conventional bias circuits such as 100 and 150 of FIGS. 1A and 1B, respectively, do not track variations in the device under the sensing. This will make the SA design very difficult and less accurate.
As such, what is desired is a SA bias circuit that can provide a reference to a device under the sensing and capability of automatically tracking variations and fluctuations therein.